KS32C50100 risc microcontroller interrupt controller 13-1 13 interrupt controller the KS32C50100 interrupt controller has a total of 21 interrupt sources. interrupt requests can be generated by internal function blocks and at external pins. the arm7tdmi core recongnizes two kinds of interrupts: a normal interrupt request (irq), and a fast interrupt request (fiq). therefore all KS32C50100 interrupts can be categorized as either irq or fiq. the KS32C50100 interrupt controller has an interrupt pending bit for each interrupt source. four special registers are used to control interrupt generation and handling: ? interrupt priority registers. the index number of each interrupt source is written to the pre-defined interrupt priority register field to obtain that priority. the interrupt priorities are pre-defined from 0 to 20. ? interrupt mode register. defines the interrupt mode, irq or fiq, for each interrupt source. ? interrupt pending register. indicates that an interrupt request is pending. if the pending bit is set, the interrupt pending status is maintained until the cpu clears it by writing a "1" to the appropriate pending register. when the pending bit is set, the interrupt service routine starts whenever the interrupt mask register is "0". the service routine must clear the pending condition by writing a "1" to the appropriate pending bit. this avoids the possibility of continuous interrupt requests from the same interrupt pending bit. ? interrupt mask register. indicates that the current interrupt has been disabled if the corresponding mask bit is "1". if an interrupt mask bit is "0" the interrupt will be serviced normally. if the global mask bit (bit 21) is set to "1", no interrupts are serviced. however, the source's pending bit is set if the interrupt is generated. when the global mask bit has been set to "0", the interrupt is serviced.
interrupt controller KS32C50100 risc microcontroller 13-2 interrupt sources the 21 interrupt sources in the KS32C50100 interrupt structure are listed, in brief, as follows: table 13-1 KS32C50100 interrupt sources index values interrupt source [20] i 2 c-bus interrupt [19] ethernet controller mac rx interrupt [18] ethernet controller mac tx interrupt [17] ethernet controller bdma rx interrupt [16] ethernet controller bdma tx interrupt [15] hdlc channel b rx interrupt [14] hdlc channel b tx interrupt [13] hdlc channel a rx interrup [12] hdlc channel a tx interrupt [11] timer 1 interrupt [10] timer 0 interrupt [9] gdma channel 1 interrupt [8] gdma channel 0 interrupt [7] uart1 receive & error interrupt [6] uart1 transmit interrupt [5] uart0 receive & error interrupt [4] uart0 transmit interrupt [3] external interrupt 3 [2] external interrupt 2 [1] external interrupt 1 [0] external interrupt 0
KS32C50100 risc microcontroller interrupt controller 13-3 interrupt controller special registers i nterrupt mode register bit settings in the interrupt mode register, intmod, specify if an interrupt is to be serviced as a fast interrupt (fiq) or a normal interrupt (irq). table 13-2 intmod register register offset address r/w description reset value intmod 0x4000 r/w interrupt mode register 0x00000000 figure 13-1 interrupt mode register (intmod) 31 2 0 19 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 18 21 x x x x x x x x x x x x x x x x x x x x x [20:0] interrupt mode bits note : each of the 21 bits in the interrupt mode enable register, intmod, corresponds to an interrupt source. when the source interrupt mode bit is set to 1, the interrupt is processed by the arm7tdmi core in fiq (fast interrupt) mode. otherwise, it is processed in irq mode (normal interrupt). the 21 interrupt sources are mapped as follows: [20] i 2 c interrupt [19] ethernet controller mac rx interrupt [18] ethernet controller mac tx interrupt [17] ethernet controller bdma rx i nterrupt [16] ethernet controller bdma tx interrupt [15] hdlc channel b rx interrupt [14] hdlc channel b tx interrupt [13] hdlc channel a rx interrupt [12] hdlc channel a tx interrupt [11] timer 1 interrupt [10] timer 0 interrupt [9] gdma channel 1 interrupt [8] gdma channel 0 interrupt [7] uart1 receive & error interrupt [6] uart1 transmit interrupt [5] uart0 receive & error interrupt [4] uart0 transmit interrupt [3] external interrupt 3 [2] external interrupt 2 [1] external interrupt 1 [0] external interrupt 0 intmod
interrupt controller KS32C50100 risc microcontroller 13-4 interrupt pending register the interrupt pending register, intpnd, contains interrupt pending bits for each interrupt source. this register has to be cleared at the top of a interrupt service routine. table 13-3 intpnd register register offset address r/w description reset value intpnd 0x4004 r/w interrupt pending register 0x00000000 figure 13-2 interrupt pending register (intpnd) 31 2 0 19 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 18 21 x x x x x x x x x x x x x x x x x x x x x [20:0] interrupt pending bits note : each of the 21 bits in the interrupt pending register, intpnd, corresponds to an interrupt source. when an interrupt request is generated, its pending bit is set to 1. the service routine must then clear the pending condition by writing a 1 to the appropriate pending bit at start. the 21 interrupt sources are mapped as follows: [20] i 2 c interrupt [19] ethernet controller mac rx interrupt [18] ethernet controller mac tx interrupt [17] ethernet controller bdma rx inter rupt [16] ethernet controller bdma tx interrupt [15] hdlc channel b rx interrupt [14] hdlc channel b tx interrupt [13] hdlc channel a rx interrupt [12] hdlc channel a tx interrupt [11] timer 1 interrupt [10] timer 0 interrupt [9] gdma channel 1 interrupt [8] gdma channel 0 interrupt [7] uart1 receive & error interrupt [6] uart1 transmit interrupt [5] uart0 receive & error interrupt [4] uart0 transmit interrupt [3] external interrupt 3 [2] external interrupt 2 [1] external interrupt 1 [0] external interrupt 0 intpnd
KS32C50100 risc microcontroller interrupt controller 13-5 interrupt mask register the interrupt mask register, intmsk, contains interrupt mask bits for each interrupt source. table 13-4 intmsk register register offset address r/w description reset value intmsk 0x4008 r/w interrupt mask register 0x003fffff figure 13-3 interrupt mask register (intmsk) 31 2 0 19 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 18 21 x x x x x x x x x x x x x x x x x x x x x 22 g [20:0] individual interrupt mask bits note : each of the 21 bits in the interrupt mask register, intmsk, (except for the global mask bit, g) corresponds to an interrupt source. when a source interrupt mask bit is 1, the interrupt is not serviced by the cpu when the corresponding interrupt request is generated. if the mask bit is 0, the interrupt is serviced upon request. and if global mask bit (bit 21) is 1, no interrupts are serviced. (however, the source pending bit is set whenever the interrupt is generated.) after the global mask bit is cleared, the interrupt is serviced. the 21 interrupt sources are mapped as follows: [20] i 2 c interrupt [19] ethernet controller mac rx interrupt [18] ethernet controller mac t x interrupt [17] ethernet controller bdma rx interrupt [16] ethernet controller bdma tx interrupt [15] hdlc channel b rx interrupt [14] hdlc channel b tx interrupt [13] hdlc channel a rx interrupt [12] hdlc channel a tx interrupt [11] timer 1 interrupt [10] timer 0 interrupt [9] gdma channel 1 interrupt [8] gdma channel 0 interrupt [7] uart1 receive & error interrupt [6] uart1 transmit interrupt [5] uart0 receive & error interrupt [4] uart0 transmit interrupt [3] external interrupt 3 [2] external interrupt 2 [1] external interrupt 1 [0] external interrupt 0 [21] global interrupt mask bit 0 = enable interrupt requests 1 = disable all interrupt requests intmsk
interrupt controller KS32C50100 risc microcontroller 13-6 interrupt priority registers the interrupt priority registers, intpri0?intpri5, contain information about which interrupt source is assigned to the pre-defined interrupt priority field. each intprin register value determines the priority of the corresponding interrupt source. the lowest priority value is priority 0, and the highest priority value is priority 20. the index value of each interrupt source is written to one of the above 21 positions (see figure 13-4). the position value then becomes the written interrupt's priority value. the index value of each interrupt source is listed in table 13-1. table 13-5 interrupt priority register overview registers offset address r/w description reset value intpri0 0x400c r/w interrupt priority register 0 0x03020100 intpri1 0x4010 r/w interrupt priority register 1 0x07060504 intpri2 0x4014 r/w interrupt priority register 2 0x0b0a0908 intpri3 0x4018 r/w interrupt priority register 3 0x0f0e0d0c intpri4 0x401c r/w interrupt priority register 4 0x13121110 intpri5 0x4020 r/w interrupt priority register 5 0x00000014 figure 13-4 interrupt priority registers (intprin) priority0 priority4 priority8 priority12 priority16 priority20 priority1 priority17 priority13 priority9 priority5 priority2 priority6 priority10 priority14 priority18 0 0 0 priority19 priority15 priority11 priority7 priority3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 0 2 1 intpri0 intpri1 intpri2 intpri3 intpri4 intpri5 high priority low priority low priority high priority
KS32C50100 risc microcontroller interrupt controller 13-7 interrupt offset register the interrupt offset register, intoffset, contains the interrupt offset address of the interrupt which has the highest priority among the pending interrupts. the content of the interrupt offset address is "bit position value of the interrupt source << 2". if all interrupt pending bits are "0" when you read this register, the return value is "0x00000054". this register is valid only under the irq or fiq mode in the arm7tdmi. in the interrupt service routine, you should read this register before changing the cpu mode. intoset_fiq/intoset_irq register can be used to get the highest priority interrupt without cpu mode change. other usages are similar to intoffset. note if the lowest interrupt priority (priority 0) is pending, the intoffset value will be "0x00000000". the reset value will, therefore, be changed to "0x00000054" (to be differentiated from interrupt pending priority 0). table 13-6 intoffset register register offset address r/w description reset value intoffset 0x4024 r interrupt offset register 0x00000054 intoset_fiq 0x4030 r fiq interrupt offset register 0x00000054 intoset_irq 0x4034 r irq interrupt offset register 0x00000054
interrupt controller KS32C50100 risc microcontroller 13-8 interrupt pending by priority register the interrupt pending by priority register, intpndpri, contains interrupt pending bits which are re-ordered by the intprin register settings. intpndpri[20] is mapped to the interrupt source of whichever bit index is written into the priority 20 field of the intprin registers. this register is useful for testing. to validate the interrupt pending by priority value, you can obtain the highest priority pending interrupt from the interrupt offset register, intoffset. table 13-7 intpndpri register register offset address r/w description reset value intpndpri 0x4028 r interrupt pending by priority 0x00000000
KS32C50100 risc microcontroller interrupt controller 13-9 interrupt pending test register the interrupt pending test register, intpndtst, is used to set or clear intpnd and intpndpri. if user writes data to this register, it is written into both the intpnd register and intpndpri register. the interrupt pending test register, intpndtst, is also useful for testing. for intpnd, the same bit position is updated with the new comming data. for intpndpri, the mapping bit position by intprin registers is updated with the new comming data to keep with the contents of the intpnd register. table 13-8 intpndtst register register offset address r/w description reset value intpndtst 0x402c w interrupt pending test register 0x00000000
interrupt controller KS32C50100 risc microcontroller 13-10 notes
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